FPGA basic knowledge question and answer 500 asked serial (2)

FPGA chips have fixed clock routing that can reduce clock jitter and skew. When phase shifting or frequency conversion of the clock is required, it is generally not allowed to perform logical operations on the clock, which not only increases the deviation and jitter of the clock, but also causes the clock to be burred. The general approach is to use the FPGA chip's own clock manager such as PLL, DLL or DCM, or to convert the logic to the D input of the flip-flop (these are also alternatives to clock logic operation).

First of all, talk about the delay implementation of asynchronous circuits: half of the asynchronous circuit is by adding buffer, two-level NAND gate, etc. (I have not used it so it is not very clear), but this is not suitable for synchronous circuit implementation delay. In the synchronous circuit, for relatively large and special-demand delays, half of the counters are generated by the high-speed clock, and the delay is controlled by the counter; for relatively small delays, one shot can be taken by the flip-flop, but this can only be delayed. One clock cycle.

Three resources: block ram; trigger (FF), lookup table (LUT);

Note: 1: When generating RAM and other storage units, block ram resources should be preferred; there are two reasons: First: using resources such as block ram, you can save more FF and 4-LUT and other low-level programmable units. Using block ram can be said to be "no need to use white", which is a manifestation of maximizing device performance and cost saving; second: block ram is a configurable hardware structure, its reliability and speed with LUT and register The built memory is more advantageous. 2: clarify the hardware structure of the FPGA, rational use of block ram resources; 3: analyze block ram capacity, use block ram resources efficiently; 4: distributed ram resources (distribute ram)

Commonly used Xilinx device primitives related to global clock resources include: IBUFG, IBUFGDS, BUFG, BUFGP, BUFGCE, BUFGMUX, BUFGDLL, DCM, and so on. An explanation of the individual device primitives can be found in section p50 of the FPGA Design Guidelines.

The HDL language is hierarchical and type. The most commonly used hierarchical concepts are system and standard, functional module level, behavior level, register transfer level and gate level.

The lookup table (look-up-table) is simply referred to as LUT, and the LUT is essentially a RAM. Currently, four input LUTs are used in FPGAs, so each LUT can be viewed as a 16x1 RAM with a 4-bit address line. When the user describes a logic circuit through the schematic or HDL language, the PLD/FPGA development software automatically calculates all possible results of the logic circuit and writes the result to the RAM in advance, so that each logical input is equivalent to one signal. Enter an address to look up the table, find out the content corresponding to the address, and then output

The design front end is also called logic design, and the back end design is also called physical design. There is no strict limit between the two. Generally, the design related to the process is the back end design.

1: Specification development: The customer proposes design requirements to the chip design company.

2: Detailed design: The chip design company (Fabless) takes out the design solution and the specific implementation architecture according to the specifications proposed by the customer, and divides the module functions. The current architecture verification is generally based on the systemC language, and the simulation of the post-valuation model can use the simulation tool of systemC. For example: CoCentric and Visual Elite.

3: HDL coding: design input tools: ultra, visual VHDL, etc.

4: Simulation verification: modelsim

5: Logic synthesis: synplify

6: Static Timing Analysis: Prime TIme for synopsys

7: Formal Verification: Synopsys' Formality.

Each component in the IC is fabricated on the same substrate, which is destined to have a parasitic effect between the component and the component. Some parasitic effects are not available in discrete circuits, so studying ICs must understand these parasitic effects, reduce the cause of parasitic effects, or eliminate parasitic effects, avoid affecting the performance of the circuit, and if possible, use certain Parasitic effects form the components required for the circuit, simplifying the design of the circuit.

For example, the measures adopted are:
Add n + buried layer 1 Increase the base width of the parasitic PNP transistor 2 Form the parasitic PNP transistor base region deceleration field

Carryout and next-stage?

Process(sig_intel)

Begin

Case sig_intel is

When "000" => carryout <= '0';

Next_state <= '0';

When "001" => carryout <= '1';

Next_state <= '0';

When "010" => carryout <= '1';

Next_state <= '0';

When "011" => carryout <= '0';

Next_state <= '1';

When "100" => carryout <= '1';

Next_state <= '0';

When "101" => carryout <= '0';

Next_state <= '1';

When "110" => carryout <= '0';

Next_state <= '1';

When "111" => carryout <= '1';

Next_state <= '1';

When others => carryout <= 'X';

Next_state <= 'X';

End case;

End process;

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