Due to the large amount of data collected by the image acquisition system and the high bandwidth requirements, the previous image acquisition system is usually implemented using the PCI bus. However, the number of PCI interfaces configured by the computer itself is very limited, and the disassembly and assembly of PCI interface devices requires opening the chassis. Generally, the operator does not have such capabilities, which limits the application of the system. The USB (Universal Serial Bus) interface series can completely solve the above problems. First of all, the speed of the USB2.0 interface has reached 480Mbps, which can fully meet the speed requirements of the image acquisition system. In addition, the USB interface is truly an interface that supports plug-and-play and allows hot-plugging, so at present a large number of data acquisition systems choose to use the USB2.0 interface to achieve. This article uses SAA7113H to realize analog video signal decoding, and uses EZ-USB FX2 single-chip CY7C68013 to transfer digital image data directly to the computer through the USB2.0 interface, through the PC program to achieve lossless image acquisition, greatly simplifying the hardware design of the acquisition card, The hardware requirements of the capture card are reduced, and the cost of the image capture card is effectively reduced. 1 System hardware design The system hardware structure is shown in Figure 1. The system is mainly composed of video decoding chip SAA7113H, USB control chip CY7C68013 and a 24C01EEPROM chip with a capacity of 1kB. Figure 1 System hardware structure 1.1 Video decoding chip-SAA7113H SAA7113H is a video decoding chip produced by Philips. Its function is to decode the input analog video signal into a standard 8-bit VPO digital signal. It can input 4 analog video signals, through the I2C bus to different configurations of internal registers can convert 4 composite video input, change the brightness, contrast and other parameters. SAA7113H is compatible with PAL, NTSC and other formats, can automatically detect the field frequency, and can automatically switch between PAL and NTSC. The SAA7113H decoded output is a standard YUV 4: 2: 2 format digital signal. 1.2 USB control chip--CY7C68013A CYTC68013A (EZ-USB FX2) is a USB2.0 chip launched by Cypress Semiconductor Corporation. It integrates an enhanced 8051 core and supports a maximum clock frequency of 48MHz. At the same clock frequency, the average instruction execution speed of FX2 can reach 2.5 times the standard 8051. The CY7C68013 chip integrates a SIE (serial interface engine) that is relatively independent of the 8051 core. Without the participation of the 8051 core, the FIFO is shared through the USB port and external logic to realize the data exchange between external data and the USB port. , Has greatly accelerated the speed of data transmission, the maximum speed that can be achieved is 480Mbps. 1.3 System hardware implementation In terms of hardware connection, use the I2C port of CY7C68013 to connect 24C01, so as to extract the information in 24C01 after the system is powered on, implement device enumeration, and download the corresponding firmware. Use the CY7C68013 analog I2C port to connect to SAA7113H, configure its internal registers, and implement the decoding chip initialization operation. CY7C68013 works in Slave FIFO (slave FIFO) mode, connects SAA7113H's VPO data bus directly to the FD bus of CY7C68013, and uses the IOAO port of CY7C68013 to detect the field mark signal of digital video for frame synchronization. The SLWR * (slave write) semaphore of CY7C68013 is valid, and SLRD (slave read) and SLOE (output valid) are invalid. SAA7113H writes the digital video signal into CY7C68013 directly in a synchronized manner through the 27MHz synchronous clock output by itself FIFO, and then directly transfer the data in the FIFO to the PC in a high-speed manner through SIE to realize the collection of video data. 2 System software design The system software design mainly includes firmware programming, driver design and PC acquisition program. 2.1 Firmware programming The firmware program flow chart is shown in Figure 2. This firmware initializes CY7C68013 after the card is powered on, making it work in Slave FIFO mode, setting the bus number to 8 bits, in order to receive the 8-bit digital video signal of SM7113H. Set EP2 endpoint to batch AUTO IN transmission mode, 512 bytes 4 times FIFO buffer. The maximum transmission packet size at one time is 512 bytes. Use the clock signal of SAA7113H to realize synchronous slave FIFO write data. Figure 2 firmware program flow chart The SAA7113H is initialized through the simulated I2C port, so that it can receive the analog video signal of the CCD camera, output in the standard ITU656 format, and set the RSTO output parity field flag, and then wait for the host computer to start the acquisition command. After receiving the image acquisition command from the PC, the firmware program first checks the parity field signal of SAA7113H through the IOAO port. If the external analog video signal source is not connected, the signal will remain high. When the firmware waits for a while and confirms that the external video signal is not connected, it returns the information that the device is not ready to the PC, otherwise it will always clear the FIFO and clear the valid data in the FIFO until the odd field signal arrives and the firmware returns the device Prepare the information to the PC to realize the synchronization of video image frame acquisition. The image data transmission process will be fully controlled by SIE, and the firmware will not participate in the transmission operation. 2.2 Driver design The Cypress development kit provides a universal driver, cyUSB.sys, which conforms to the WHQL standard of the Windows Hardware Quality Lab. The system uses this driver to implement image data acquisition directly. Because CY7C68013 adopts a soft configuration scheme, the chip does not provide a memory for permanently storing the firmware program. The firmware program needs to be loaded through the external memory or downloaded from the PC to the internal RAM after each power-on. The driver mainly implements the loading function of the firmware program, so that after the system is powered on, it can automatically download the firmware from the PC to the CY7C68013, and then use the universal driver to complete the enumeration of the device of the capture card. The development package provided by CyprESS contains a firmware download driver template, that is, EZ-Loader Driver. The system firmware download driver mainly depends on it. The specific steps are: 1) Use hex2c.exe to convert the Intel HEX format file into a C code array. 2) Copy all EZ-Loader Driver files and sub-files into a newly created directory. And use the C code array obtained in the first step to replace the array in firmwa re.c in EZ-Loader Driver. 3) Use the build command in the WindowsXP DDK to create the firmware download driver in the new directory. 4) Rewrite the driver installation information file.
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